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1 mx25l5121e, mx25l1021e datasheet mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
2 contents features .................................................................................................................................................................. 4 general ............................................................................................................................................................ 4 performance ................................................................................................................................................. 4 software features ..................................................................................................................................... 4 hardware features ..................................................................................................................................... 4 general description ......................................................................................................................................... 5 pin configurations ............................................................................................................................................. 6 pin description ...................................................................................................................................................... 6 block diagram ....................................................................................................................................................... 7 memory organization ......................................................................................................................................... 8 table 1-1. memory organization (512kb) ........................................................................................................... 8 table 1-2. memory organization (1mb) ............................................................................................................... 8 device operation .................................................................................................................................................. 9 figure 1. serial modes supported ........................................................................................................................ 9 data protection .................................................................................................................................................. 10 table 2. protected area sizes ............................................................................................................................ 10 command description ....................................................................................................................................... 11 table 3. command set ....................................................................................................................................... 11 (1) write enable (wren) ................................................................................................................................... 12 (2) write disable (wrdi) .................................................................................................................................... 12 (3) read identifcation (rdid) ............................................................................................................................ 12 table 4. id defnitions ....................................................................................................................................... 12 (4) read status register (rdsr) ...................................................................................................................... 13 table 5. status register ..................................................................................................................................... 13 (5) write status register (wrsr) ...................................................................................................................... 14 table 6. protection modes .................................................................................................................................. 14 (6) read data bytes (read) ............................................................................................................................. 15 (7) read data bytes at higher speed (fast_read) ....................................................................................... 15 (8) sector erase (se) ......................................................................................................................................... 15 (9) block erase (be) ........................................................................................................................................... 15 (10) chip erase (ce) .......................................................................................................................................... 16 (11) page program (pp) ..................................................................................................................................... 16 (12) deep power-down (dp) ............................................................................................................................. 16 (13) release from deep power-down (rdp) .................................................................................................... 17 power-on state ................................................................................................................................................... 18 program/ erase fow with read array data .......................................................................................................... 19 electrical specifications .............................................................................................................................. 20 mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
3 absolute maximum ratings ..................................................................................................................... 20 figure 2. maximum negative overshoot waveform .......................................................................................... 20 capacitance ta = 25c, f = 1.0 mhz ............................................................................................................. 20 figure 3. maximum positive overshoot waveform ............................................................................................ 20 figure 4. input test waveforms and measurement level .............................................................. 21 figure 5. output loading ........................................................................................................................... 21 table 7. dc characteristics (temperature = 0 c to 70 c for commercial grade, vcc = 2.7v ~ 3.6v) .. 22 table 8. ac characteristics (temperature = 0c to 70c for commercial grade, vcc = 2.7v ~ 3.6v) . 23 timing analysis ........................................................................................................................................................ 24 figure 6. serial input timing .............................................................................................................................. 24 figure 7. output timing ...................................................................................................................................... 24 figure 8. wp# disable setup and hold timing during wrsr when srwd=1 ................................................. 25 figure 9. write enable (wren) sequence (command 06) ............................................................................... 25 figure 10. write disable (wrdi) sequence (command 04) .............................................................................. 25 )ljxuh5hdg,ghqwlfdwlrq5','6htxhqfh&rppdqg) ...................................................................... 26 figure 12-1. read status register (rdsr) sequence (command 05) ............................................................. 27 figure 12-2. read status register (rdsr) sequence (command 05) ............................................................. 27 figure 13. write status register (wrsr) sequence (command 01) ............................................................... 28 figure 14. read data bytes (read) sequence (command 03) ...................................................................... 28 figure 15. read at higher speed (fast_read) sequence (command 0b) ................................................... 29 figure 16. sector erase (se) sequence (command 20) .................................................................................. 29 figure 17. block erase (be) sequence (command d8 or 52) .......................................................................... 30 figure 18. chip erase (ce) sequence (command 60 or c7) ........................................................................... 30 figure 19. page program (pp) sequence (command 02) ................................................................................ 30 figure 20. deep power down (dp) sequence (command b9) ........................................................................ 31 figure 21. release from deep power down (rdp) sequence (command ab) ............................................... 31 figure 23. power-up timing ............................................................................................................................... 32 table 9. power-up timing .................................................................................................................................. 32 initial delivery state ................................................................................................................................. 32 operating conditions ....................................................................................................................................... 33 figure 24. ac timing at device power-up ......................................................................................................... 33 figure 25. power-down sequence .................................................................................................................... 34 erase and programming performance .................................................................................................... 35 data retention ................................................................................................................................................... 35 latch-up characteristics .............................................................................................................................. 35 ordering information ...................................................................................................................................... 36 part name description ..................................................................................................................................... 37 package information ........................................................................................................................................ 38 revision history ................................................................................................................................................. 41 mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
4 512k-bit [x 1] cmos serial flash memory 1m-bit [x 1] cmos serial flash memory features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 512k: 524,288 x 1 bit structure 1m: 1,048,576 x 1 bit structure ? 16 equal sectors with 4k bytes each (512kb) 32 equal sectors with 4k bytes each (1mb) - any sector can be erased individually ? 1 equal blocks with 64k byte each ( 512kb ) 2 equal blocks with 64k byte each (1mb) - any block can be erased individually ? program capability - byte base - page base (32 bytes) ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v performance ? performance - fast read: 45mhz serial clock - fast program time: 180us(typ.) and 650us(max.)/page - fast erase time: 40ms (typ.)/sector ; 1s (typ.)/block ? low power consumption - low active read current: 5ma(max.) at 25mhz, 10ma(max.) at 45mhz - low active programming current: 8ma (typ.) - low active erase current: 10ma (typ.) - low standby current: 20ua (typ.) - deep power down current: 2ua (typ.) ? typical 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? block lock protection - the bp0~bp1 status bits defnes the size of the area to be software protected against program and erase instructions ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) ? status register feature ? electronic identifcation - jedec 1-byte manufacturer id and 2-bytes device id hardware features ? sclk input - serial clock input ? si input mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
5 general description the device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. the device provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fed page or sector locations will be executed. program command is executed on page (32 bytes) basis, and erase command is executes on sector, or block, or whole chip. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. when the device is not in operation and cs# is high, it is put in standby mode. the device utilizes macronix proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. - serial data input ? so output - serial data output ? wp# pin - hardware write protection ? package - 8-pin sop (150mil) - 8-pin tssop (173mil) - 8-uson (2x3mm) - all devices are rohs compliant and halogen-free mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
6 pin configurations pin description 8-pin tssop (173mil) symbol description cs# chip select si serial data input (for 1 x i/o) so serial data output (for 1 x i/o) sclk clock input nc nc pin (not connect) wp# write protection vcc 2.7v to 3.6v power supply gnd ground 1 2 3 4 cs# so wp# gnd vcc nc sclk si 8 7 6 5 8-pin sop (150mil) 1 2 3 4 cs# so wp# gnd vcc nc sclk si 8 7 6 5 8-land uson (2x3mm) 1 2 3 4 cs# so wp# gnd 8 7 6 5 vcc nc sclk si mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
7 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si sclk so clock generator state machine mode logic sense amplifier hv generator output buffer cs# mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
8 table 1-1. memory organization (512kb) table 1-2. memory organization (1mb) memory organization block sector address range 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh block sector address range 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
9 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, all so pins of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 1. 5. for the following instructions: rdid, rdsr, read and fast_read the shifted-in instruction sequence is fol - lowed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, pp, rdp, and dp the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of program, erase operation, to access the memory array is neglected and not affect the current operation of program and erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
10 data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. ? software protection mode (spm): by using bp0-bp1 bits to set the part of flash protected from data change. ? hardware protection mode (hpm): by using wp# going low to protect the bp0-bp1 bits and srwd bit from data change. ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp). table 2. protected area sizes status bit protect level bp1 bp0 mx25l5121e mx25l1021e 0 0 0 (none) 0 (none) 0 1 1 (all) 1 (1 block) 1 0 2 (all) 2 (all) 1 1 3 (all) 3 (all) mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
11 command description table 3. command set command (byte) wren (write enable) wrdi (write disable) wrsr (write status register) rdid (read identifc- ation) rdsr (read status register) read (read data) fast read (fast read data) 1st byte 06 (hex) 04 (hex) 01 (hex) 9f (hex) 05 (hex) 03 (hex) 0b (hex) 2nd byte ad1 (a23-a16) ad1 3rd byte ad2 (a15-a8) ad2 4th byte ad3 (a7-a0) ad3 5th byte dummy action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to write new values of the status register outputs jedec id: 1-byte manufacturer id & 2-bytes device id to read out the values of the status register n bytes read out until cs# goes high n bytes read out until cs# goes high command (byte) se (sector erase) be (block erase) ce (chip erase) pp (page program) dp (deep power down) rdp (release from deep power down) 1st byte 20 (hex) 52 or d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) 2nd byte ad1 ad1 ad1 3rd byte ad2 ad2 ad2 4th byte ad3 ad3 ad3 action to erase the selected sector to erase the selected block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode note 1: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hidden mode. note 2: value "1" should be input to the un-used signifcant bits of address bits by user (e.g. a17~a23(msb) in mx25l1021e ; a16-a23(msb) in mx25l5121e) mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
12 (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce and wrsr which are intended to change the device content, should be set every time after the wren in - struction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction codecs# goes high. (please refer to figure 9 ) (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsendi ng wrdi instruction codecs# goes high. (please refer to figure 10 ) the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion (3) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-bytes. the mxic manufacturer id is c2(hex), the memory type id is 22(hex) as the frst-byte device id, and the individual device id of second-byte id are listed as table of "id defnitions". (please refer to table 4) the sequence of issuing rdid instruction is: cs# goes lowsending rdid instruction code24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. (please refer to figure 11 ) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby mode. table 4. id defnitions rdid command mx25l5121e mx25l1021e manufacturer id memory type memory density manufacturer id memory type memory density c2 22 10 c2 22 11 mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
13 (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program or erase operation is in progress. the sequence of issuing rdsr instruction is: cs# goes lowsending rdsr instruction codestatus register data out on so (please refer to figure 12-1 , figure 12-2 ) the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase progress. when wip bit sets to 1, which means the device is busy in program/erase progress. when wip bit sets to 0, which means the device is not in progress of program/erase register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase instruction. bp1, bp0 bits. the block protect (bp1, bp0) bits, volatile bits, indicate the protected area(as defned in table 1) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase(ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed) srwd bit. the status register write disable (srwd) bit, volatile bit, is operated together with write protection (wp#) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp# pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer ac - cepted for execution and the srwd bit and block protect bits (bp1, bp0) are read only. table 5. status register note: 1. see the table "protected area sizes". the default bp0-bp2 values are "1" (protected). 2. the srwd default value is "0" bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) reserved reserved reserved bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 0 0 0 (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
14 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp1, bp0) bits to defne the protected area of memory (as shown in table 1). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on si cs# goes high. (see figure 13 ) the wrsr instruction has no effect on b6, b5, b4, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 6. protection modes note: 1. as defned by the values in the block protect (bp1, bp0) bits of the status register, as shown in table 1. as the table above showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp# is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp1, bp0. the protected area, which is defned by bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp1, bp0. the protected area, which is defned by bp1, bp0, is at software protected mode (spm) note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previ - ously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp# is low (or wp# is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp1, bp0 and hard - ware protected mode by the wp# to against data modifcation. note: to exit the hardware protected mode requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp1, bp0. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp1 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp1 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
15 (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fc. the frst address can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. this product does not provide the function of read around. after reading through density 512kb or 1mb, cs# must go high. otherwise, the data correctness will not be guaranteed. if the device needs to read data again, it must issue read command once more. the sequence of issuing read instruction is: cs# goes low sending read instruction code 3-bytes address on sidata out on soto end read operation can use cs# to high at any time during data out. (please refer to figure 14 ) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si 1-dummy byte address on sidata out on so to end fast_read operation can use cs# to high at any time during data out. ( please refer to figure 15 ) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (8) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-bytes sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit be - fore sending the sector erase (se). any address of the sector (please refer to table 1) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes lowsending se instruction code3-bytes address on si cs# goes high. (please refer to figure 16 ) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. (9) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte sector erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
16 bit before sending the block erase (be). any address of the block (see table 2) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence is shown as figure 17 . the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. (10) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 1) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex - ecuted. the sequence is shown as figure 18 . the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. (11) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). after the instruction and address input, data to be programmed is input sequentially. the internal sequence controller will sequentially program the data from the initial address. if the transmitted data goes beyond the page boundary, the internal se - quence controller may not function properly and the content of the device will not be guaranteed. therefore, if the initial a4-a0 (the fve least signifcant address bits) are set to all 0, maximum 32 bytes of data can be input sequen - tially. if the initial address a4-a0 (the fve least signifcant address bits) are not set to all 0, maximum bytes of data input will be the subtraction of the initial address a4-a0 from 32bytes. the data exceeding 32bytes data is not sent to device. in this case, data is not guaranteed. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-bytes address on si at least 1-byte on data on si cs# goes high. (please refer to figure 19 ) the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. (12) deep power-down (dp) the deep power down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power down mode), the standby current is reduced from isb1 to isb2. the deep power down mode requires the deep power down (dp) instruction to enter, during the deep power down mode, the device is not ac - mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
17 tive and all read/write/program/erase instruction are ignored. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction code cs# goes high. (please refer to figure 20 ) once the dp instruction is set, all instruction will be ignored except the release from deep power down mode (rdp) instruction. when power-down, the deep power down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power down mode. (13) release from deep power-down (rdp) the release from deep power down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the standby mode. if the device was not previously in the deep power down mode, the transition to the standby mode is immediate. if the device was previously in the deep power down mode, though, the transition to the standby mode is delayed by tres1, and chip select (cs#) must remain high for at least tres1(max), as specifed in table 8 . ac characteristics. once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. the sequence is shown as figure 21 . even in deep power down mode, the rdp is also allowed to be executed, only except the device is in progress of program/erase cycle; there's no effect on the current program/erase cycle in progress. mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
18 power-on state the device is at below states when power-up: - standby mode ( please note it is not deep power down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uf) mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013

20 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, please refer to figure 2, 3. absolute maximum ratings electrical specifications capacitance ta = 25c, f = 1.0 mhz figure 2. maximum negative overshoot waveform figure 3. maximum positive overshoot waveform rating value ambient operating temperature commercial grade 0c to 70c storage temperature -65c to 150c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
21 figure 4. input test waveforms and measurement level figure 5. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.2vcc note: input pulse rise and fall time are <8ns 0.7vcc 0.3vcc device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf including jig capacitance notes: rise time means 0.2vcc to 0.8vcc; fall time means 0.8vcc to 0.2vcc. mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
22 table 7. dc characteristics (temperature = 0 c to 70 c for commercial grade, vcc = 2.7v ~ 3.6v) notes : 1. typical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. 3. not 100% tested. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 20 30 ua vin = vcc or gnd, cs# = vcc isb2 deep power down current 2 8 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 10 ma f=45mhz, sclk=0.1vcc/0.9vcc, so=open 5 ma f=25mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 8 12 ma program in progress, cs# = vcc icc3 vcc write register (wrsr) current 1 15 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 10 15 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua vwi low vcc write inhibit voltage 3 2.1 2.3 2.5 v mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
23 table 8. ac characteristics (temperature = 0c to 70c for commercial grade, vcc = 2.7v ~ 3.6v) notes: 1. tch + tcl must be greater than or equal to 1/ f (fc). 2. value guaranteed by characterization, not 100% tested in production. 3. test condition is shown as figure 4, 5. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for fast_read dc 45 mhz frsclk fr clock frequency for the following instructions: read, pp, se, be, ce, dp, rdp, wren, rdid, rdsr, wrsr dc 25 mhz tch(1) tclh clock high time @ 25 mhz 18 ns @ 45 mhz 10 ns tcl(1) tcll clock low time @ 25 mhz 18 ns @ 45 mhz 10 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns trise(2) clock rise time (3) 10 ns/v tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tfall(2) clock fall time (3) 10 ns/v tslch tcss cs# active setup time (relative to sclk) 20 ns tchsl cs# not active hold time (relative to sclk) 20 ns tdvch tdsu data in setup time 4 ns tchdx tdh data in hold time 6 ns tchsh cs# active hold time (relative to sclk) 20 ns tshch cs# not active setup time (relative to sclk) 20 ns tshsl(3) tcsh cs# deselect time read 50 ns write/erase/program 50 ns tshqz(2) tdis output disable time 20 ns tclqv tv clock low to output valid @ 25 mhz 18 ns @ 45 mhz 18 ns tclqx tho output hold time 0 ns twhsl(4) write protect setup time 20 ns tshwl(4) write protect hold time 100 ns tw write status register cycle time 5 15 ms tdp(2) cs# high to deep power down mode 20 us tres1(2) cs# high to standby mode without electronic signature read 20 us tpp page program cycle time (32 bytes) 150 650 us tse sector erase cycle time (4k bytes) 40 300 ms trpd1 cs# high to power-down 100 ns tbe block erase cycle time 1 2 s tce chip erase cycle time 512kb 1 2 s 1mb 1.5 3 s mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
24 figure 6. serial input timing figure 7. output timing timing analysis sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
25 figure 8. wp# disable setup and hold timing during wrsr when srwd=1 high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so figure 9. write enable (wren) sequence (command 06) figure 10. write disable (wrdi) sequence (command 04) 2 1 34567 high-z 0 06 command sclk si cs# so 2 1 34567 high-z 0 04 command sclk si cs# so mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
26 figure 11. read identifcation (rdid) sequence (command 9f) 2 1 3456789 10 11 12 13 14 15 command 0 manufacturer id high-z msb 15 14 13 3210 device id msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
27 figure 12-1. read status register (rdsr) sequence (command 05) 2 1 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 figure 12-2. read status register (rdsr) sequence (command 05) 7 6543210 sclk si 05 cs# so command status register out msb high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6543210 sclk si 05 cs# so command status register out msb high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6543210 sclk si 05 cs# so command status register out msb high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
28 figure 14. read data bytes (read) sequence (command 03) sclk si cs# so 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command figure 13. write status register (wrsr) sequence (command 01) 2 1 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
29 figure 15. read at higher speed (fast_read) sequence (command 0b) 23 2 1 3456789 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0b command figure 16. sector erase (se) sequence (command 20) 24 bit address 2 1 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
30 figure 17. block erase (be) sequence (command d8 or 52) note: be command is d8(hex). 24 bit address 2 1 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8 command figure 18. chip erase (ce) sequence (command 60 or c7) note: ce command is 60(hex) or c7(hex). 2 1 34567 0 60 or c7 sclk si cs# command figure 19. page program (pp) sequence (command 02) 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 32 287 286 285 284 283 282 281 765432 0 1 280 msb msb msb msb msb sclk cs# si sclk cs# si 02 command mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
31 figure 20. deep power down (dp) sequence (command b9) 2 1 34567 0 t dp deep power down mode standby mode sclk cs# si b9 command figure 21. release from deep power down (rdp) sequence (command ab) 2 1 34567 0 t res1 standby mode deep power down mode high-z sclk cs# si so ab command mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
32 figure 23. power-up timing note: vcc (max.) is 3.6v and vcc (min.) is 3.0v. v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. the parameter is characterized only. table 9. power-up timing symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 300 us mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
33 notes : 1. sampled, not 100% tested. 2. for ac spec tslch, tdvch, tchdx, tchsh in the fgure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 10 500000 us/v trh reset high time before read 5 ms operating conditions at device power-up and power-down ac timing illustrated in figure 24 and figure 25 are for the supply voltages and the control signals at device power- up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 24. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
34 figure 25. power-down sequence c s # sclk v c c during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
35 erase and programming performance note: 1. typical program and erase time assumes the following conditions: 25 c, 3.3v, and checker board pattern. 2. under worst conditions of 70 c and 2.7v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. 4. erase/program cycles comply with jedec jesd-47e & a117a standard. latch-up characteristics parameter min. typ. (1) max. (2) unit sector erase time 40 300 ms block erase time 1 2 s chip erase time 512kb 1 2 s 1mb 1.5 3 s page program time 150 650 us erase/program cycle 100,000 cycles min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. data retention parameter condition min. max. unit data retention 70?c 20 years mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
36 ordering information part no. clock (mhz) temperature package remark mx25l5121emc-20g 45 0 c~70 c 8-sop (150mil) mx25l5121eoc-20g 45 0 c~70 c 8-tssop (173mil) mx25l5121ezuc-20g 45 0 c~70 c 8-uson (2x3mm) 512kb part no. clock (mhz) temperature package remark mx25l1021emc-20g 45 0 c~70 c 8-sop (150mil) 1mb mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
37 part name description mx 25 l 20 m c g option: g: rohs compliant & halogen-free speed: 20: 45mhz temperature range: c: commercial (0c to 70c) package: m: 150mil 8-sop o: 173mil 8-tssop zu: 2x3mm 8-uson density & mode: 5121e: 512kb 1021e: 1mb type: l: 3v device: 25: serial flash 1021e mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
38 package information mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
39 mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
40 mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
41 revision history revision no. description page date 0.01 1. corrected 25l5121 id code p12 apr/07/2010 2. added vwi into table 7 p22 3. modifed isb1, isb2, icc1, icc2 & icc4 p4,22,36 4. modifed tdvch, tchdx & tclqv p23 5. modifed epn p36,37 1.0 1. removed "advanced information" p4 nov/02/2011 2. modifed chip erase time (1mb) p23,35 3. modifed "at device power-up and power-down" description p33 4. modifed ilo test conditions from vin to vout p22 5. added 8-uson package information p5,6,36,37,40 1.1 removed "advanced information". p5,6,36,37 dec/29/2011 modifed storage temperature to "-65 c to 150 c" p20 1.2 modified fsclk & frsclk (min.) p23 oct/11/2013 1.3 1. updated parameters for dc/ac characteristics p4,22,23 nov/11/2013 2. updated erase and programming performance p4,35 mx25l5121e mx25l1021e p/n: pm1573 rev. 1.3, nov. 11, 2013
42 mx25l5121e mx25l1021e macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2010~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com

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